An FPGA-based Convolutional Neural Network Accelerator for Edge Computing

Convolutional Neural Networks (CNNs) are a powerful tool in computer vision, excelling at tasks like image classification and object detection. The need for low latency and strict power consumption in real-world applications during forward inference makes deploying neural networks on resource-constrained hardware challenging. This paper tackles deployment challenges by proposing Quantization-Aware Filter Pruning (QAFP), significantly reducing model size with minimal accuracy loss. Leveraging the strengths of convolutional computations, parameters are stored in blocks and optimized loop circuits are designed to maximize resource utilization on hardware. This work proposes an FPGA-based CNN accelerator that significantly improves the speed and power efficiency of CNN inference compared to traditional processors. The accelerator was evaluated on a ZYNQ XC7Z020 platform utilizing a compressed VGG16 model for validation. Notably, the compressed model achieved a high accuracy of 93.5 % while reducing the single-inference fixed-point operation count to 3.1 G (from original VGG16) and the parameter count to 1.1 M. This results in an impressive effective computing performance of 41 Giga Operations Per Second (GOP/s) while maintaining low power consumption at just 1.1 W, making it highly suitable for resource-constrained applications.