High-Speed FPGA Implementation of Modular Multiplication Over Prime Field

Multiplication over prime fields is an essential operation in public key cryptosystems, significantly impacting overall system performance in terms of both area usage and speed. Given its frequent replication, optimizing this operation is vital. Interleaved Modular Multiplication (IMM) based on radix-4 data encoding has shown promising performance in terms of area and latency. However, the frequency of these designs is often limited by the addition of large numbers. This study presents a novel hardware architecture that eliminates the need for precomputed values or embedded FPGA resources. It optimizes operating frequency by incorporating components with reduced critical path delays for modular operations such as doubling, quadrupling, and addition/subtraction. The design is fully reconfigurable, supporting any value and size of prime field to enhance adaptability. The design has been implemented using the Vivado 2019.2 design tool, targeting the Xilinx Virtex7 platform. The implementation achieves the lowest Area-Time Product (ATP) values of 0.6, 1.4, 2.9, and 5.5 (LUTs×ms) for 192-bit, 256-bit, 384-bit, and 521-bit sizes, respectively. These results demonstrate a balanced trade-off between area and time performance, making the design well-suited for high-speed cryptographic applications.