Rate Coding With 3D Memristor Crossbar

The SNN rate coding hardware implementation requires a dedicated circuitry to count the number of spikes from the output neurons to determine the predicted class. Monitoring the number of spikes is inefficient in larger networks. This paper proposes analog 3D super-resolution memristor crossbar for counting the output spikes during SNN rate coding. Conventional counters based on the clocked mechanism demand more area and power when the number of bits or count states increases. Further, in conventional systems, count states are erased when the power is interrupted. The proposed crossbar was designed using a 1Transistor1Memristor (1T1M) node and bridge configured 2Transistor5Memristor(2T5M) super-resolution node. When spikes are generated, the counter node is programmed, and the conductance states are encoded as count values. The bridge configuration addresses the challenge of the limited number of conductance states of the IT1M node. The proposed counter was evaluated by training the SNN using rate coding, and generated spikes were counted. The hardware implementation of the SNN was performed using a three-dimensional memristive crossbar array. The hardware implementations and the ReRAM memristor model are based on the Skywater 130 open-source PDK. The on-chip area and power were calculated for the same. The proposed counter for the SNN retains the same area and power consumption, even if the number of spikes and count states increases. Robustness of the proposed system to aging, conductance and power variability is also analysed.