Digital Implementation of Discontinuous PWMs: Mitigating Parasitic Active Vectors for Improved Load Current Quality in Inverter Systems

Discontinuous PWM (DPWM) strategies are widely used in voltage-source inverters (VSIs) due to reduced switching losses and improved harmonic performance at higher modulation indexes. However, DPWMs with discontinuous zero-sequence signals (ZSS) can cause current spikes at clamping instants, which depend on the modulation index and load parameters. In the literature, this behavior is often attributed to the rapid changes in ZSS. This article demonstrates that the current spikes are primarily caused by improper modulator implementation on digital signal processors (DSPs), which introduces an unintended active vector instead of a zero vector at the end of a positive bus clamp for a given phase. The issue arises because PWM modules operate as set-reset units based on a timer and compare values, unlike analog comparators, which react instantaneously. We propose a simple solution using an auxiliary compare register, which is effective for most DSPs. The solution's effectiveness is demonstrated on a VSI-fed 12-kW induction machine controlled by a C2000 Texas Instruments DSP.