Q-Factor Enhanced Digitally Programmable Capacitor With Parallel-Connected Structure for High RF Power Handling Applications

This article presents a comprehensive analysis of the parallel structure proposed in our previous paper for digitally programmable capacitors (DPCs). The study reveals that the parallel structure improves the Q-factor only when the capacitance difference between the ON- and OFF-states exceeds a specific threshold, referred to as the criterion capacitance. This phenomenon occurs because the Q-factor of the parallel structure deteriorates when the low Q-factor path, attributed to the parasitic capacitances of the transistor and the gate/body biasing resistor, becomes more dominant than the high Q-factor path formed by high Q-factor fixed capacitors. This dominance arises when the capacitance difference is small. Therefore, defining the criterion capacitance is critical, and an algorithm is proposed to determine this value without requiring extensive simulations. Subsequently, the relationship between the switching time and the Q-factor of the parallel structure is analyzed, and methods for further enhancing the Q-factor in applications with less critical switching time requirements are presented. To validate the proposed algorithm for calculating the criterion capacitance, a single-bit DPC with a Q-factor of 50 was fabricated. In addition, the general applicability of the parallel structure in DPCs was verified by fabricating a 3-bit DPC with a step capacitance of 300 fF and a 5-bit DPC with a step capacitance of 100 fF to confirm its suitability for high-resolution step capacitance. The Q-factor enhancement was demonstrated for both multibit DPCs. For a fair comparison, the series and parallel structures of single bits within the multibit designs, with identical capacitance differences, were designed with equivalent chip areas, and all bits were designed to maintain the same power handling capability. Measurement results showed that the parallel structure improved the Q-factor by 8.1%–154.1% for the 3-bit DPC and by 20.1%–151.0% for the 5-bit DPC at 2 GHz, compared to the series structure. The power handling capability of all four multibit DPCs was verified to be 39.6 dBm at 2 GHz.