A Tiny 3.15–43.4-GHz 3.6-mW Divide-by-8 Ring-Based Injection-Locked Frequency Divider Using Multiphase Waveform Gating Technique

To support high-speed complex modulation in the 5 G mm-wave bands (i.e. $24.25-43.5 \mathrm{GHz}$), mm-wave PLLs should provide low rms jitter while consuming low power [1]. To ensure their robust operation across such a wide frequency span, a key issue is to guarantee the proper functionality of the divider chain to correctly down-convert the oscillator’s mm-wave signal to the neighborhood frequency of the reference clock. As the first (i.e. mm-wave) divider stage, a current-mode logic (CML) divider or an injection-locked frequency divider (ILFD) is usually chosen but they suffer from high dc power or a limited locking range (LR), respectively [2–3]. Despite an acceptable LR [4–7], the division ratio is usually less than 5. To avoid the additional power/area penalty of subsequent divider stages, a high division-ratio ILFD (e.g. $\div 8$) with a wide LR is desired. Figure 1(a) presents a conventional high-division-ratio ILFD based on an N stage delay cell, but the injecting signal is only fed to the tail transistor of the first-stage delay cell, thereby offering only a limited LR.