A 10.5 Gbps 0.55 pJ/bit PAM-3 Transceiver Using a Self-driven Dual TIA Receiver and Floating Impedance Matching for Parallel On-chip Transmission Lines

The demand for high-bandwidth and parallel interconnection for memory interfaces is steadily increasing [1]–[5]. The top of Fig. 1 shows three popular structures for the memory interface. Non-return to zero (NRZ) signaling with a termination resistor has the simplest structure. However, NRZ signaling suffers from significant channel loss and power consumption due to the high clock frequency. Pulse amplitude modulation (PAM) has been proposed to extend the data rate by sending multi-bit per unit interval. However, PAM-4 consumes significant static current for intermediate levels and has a poor signal-to-noise ratio (SNR). Thus, complicated equalizing techniques are employed, leading to significant power consumption. However, PAM-3 offers a higher SNR, and removes the reference voltage (VREF) using inverter-based TIA, which makes PAM-3 transceivers more area- and power-efficient than PAM-4. However, the large static current at the Mid-level is still the fundamental limitation of PAM-3. Therefore, this paper proposes the self-driven receiver (SDR) to remove the static current in the PAM-3 transmitter (Tx) by deactivating it. The floating impedance matching (FIM) for the Mid-level reduces the channel reflections at the deactivated Tx. Finally, the dual TIAs in SDR improve signal integrity by separating the top and bottom eyes, and reduce power consumption by employing biased inverters.