A mmWave Passive CMOS Circulator with Boosted Clock Signals for Enhanced Power Handling

This paper presents a compact and wideband passive CMOS circulator designed for high-power mmWave applications. The proposed circulator is an enhanced power handling version of our previously implemented circulator based on switched all-pass filters. The key improvement is the addition of a clock booster in the LO path, which enhances the linearity and thereby the power handling of the transistor switches used in the non-reciprocal branch. The higher voltage swing provided by the clock-boosting translates to an impressive 12-dB increase in 1-dB input compression point (IP1dB) and a 10-dB increase in third-order input intercept point (IIP3) for the proposed circulator. The circuit is designed in a 28-nm CMOS process, with an active die area of only $0.17 \text{mm}^{2}$. Our simulations demonstrate that the circulator exhibits an insertion loss of 3.6 dB with a 1-dB bandwidth of 16–30 GHz, isolation of >25 dB, IP1dB of >24 dBm, and IIP3 of >30 dBm over the same wide bandwidth. The simulation results indicate that the proposed clock-boosting structure can effectively enhance the IP1dB and IIP3 of the circulator to significantly higher levels than those of the state-of-the-art circulators. At the same time, our design mitigates potential reliability issues associated with the clock-boosting techniques previously published in the literature.