A 12b 3 GS/s Passive T/H Assisted Time-Interleaved Pipelined SAR ADC with Metastability Reduction Technique and Dynamic-Bias RA

Time-interleaved (TI) ADCs present an ingenious solution to accelerate conversion rates with minimal power penalty. However, mismatches from interleaved channels, such as gain, offset, timing mismatches, are main challenges. In particular, timing mismatches, including skew and bandwidth mismatches, are nontrivial to tackle when aiming for input-independent calibration. Analog skew detection techniques [1], randomization of the interleaved channels [2–3], power-hungry full-speed track-and-hold (T/H) [3] and dither injection in the input buffer [4–5] have been developed to tackle this issue. This work utilizes a power-efficient passive T/H with less overhead. Another fundamental limitation of high-speed SAR ADCs is high CER due to comparator metastability. Prior works [6–7] processes metastability detection with the accurate information of comparator decision time (CDT) at the cost of circuit complexity. The proposed metastability reduction technique can remarkably reduce CER with a little additional delay. Operating at $3 \mathrm{GS} / \mathrm{s}$, this prototype ADC achieves a FoMw of $15.5 \mathrm{fJ} /$ conversion-step.