Graph Theory-Based Sneak Circuit Time-Domain Analysis and Trigger of CLLC Resonant Converter With Parasitic Parameters

The sneak circuits caused by internal parasitic parameters can lead to unexpected phenomena and affect the efficiency and reliability of CLLC resonant converter. Therefore, the characteristic analysis, trigger mechanism and suppression method of CLLC converter sneak circuit based on graph theory are proposed in this paper. The complete current based sneak circuit model and accurate CLLC time domain model are established. Then, the possible sneak circuit phenomena are described in detail to explain their negative effects on the converter operating characteristics, the trigger mechanism of sneak operating modes is put forward, and the suppression conditions are derived. By optimizing the parameter design and modulation parameters of CLLC converter, the unexpected sneak circuits can be avoided. Finally, the correctness of theoretical analysis is verified by experiment results, and the proposed suppression method avoids unnecessary power loss and suppresses the waveform oscillations.