An Efficient Ripple Carry Adder Using Pipelining

The Ripple Carry Adder (RPA) is a standard and reliable n-bit adder which uses a combination of Full Adders to sequentially add each bit and give the sum of the n-bit addition as the output. This Ripple Carry Adder has been used for many years in a variety of electronic applications for mathematical and other purposes, but since the advancement of technologies it is eminent to have a circuit that draws only a moderate and reasonable amount of power and also does the computation in a very efficient and fast paced manner. This can be achieved using the process of pipelining the circuit more specifically Fine Grain Pipelining. In pipelining the dependent variables are stored in registers which are controlled by a clock which will send the data in a uniform procedure and ensure the reduction in Total Time Delay of the circuit. When the Total Time Delay is reduced then the computational speed of the ripple carry adder will increase, hence making it more agile and favourable to be used in more combinational circuits. In the paper, the Ripple Carry Adder is designed and simulated with and without various levels of pipelining to find a circuit with the highest performance, the lowest critical path, and reasonable power drawn. The proposed Low Time Delay Circuit of the 4-bit Ripple Carry Adder design by integrating Fine Grain Pipelining method was designed and simulated on AMD Vivado 2023.2 and achieved a Total Time Delay of the critical path of 4.680 ns, which is lesser than the Unpipelined Ripple Carry Adder Structure. The proposed design using Fine Grain Pipelining can also be integrated with great ease to n-bit Ripple Carry Adder structures due to the flexibility and easy modular ability of the Fine Grain Pipelining.