Standard Cell Library Design for VLSI Education Using GPDK045 Considering fixed Poly Pitch and Abutment

In this paper, we discuss a novel approach to teaching students VLSI (Very Large-Scale Integration) design. We propose utilizing GPDK045 in Cadence™ Virtuoso, to offer students practical experience in VLSI design. We outline layout methodologies, design techniques and verification processes tailored to enhance student learning. The work covers fundamental logic gate creation, area optimization and industry-standard verification procedures. By providing hands on experience with professional EDA tools, this research aims to prepare students for the challenges of modern integrated circuit design. We discuss the pedagogical benefits of this approach and its potential impact on VLSI education.