Design of Josephson Junction based Reconfigurable N – point Bit slicing FFT Processor Using Mixed Radix algorithm

This research presents the design and implementation of a reconfigurable N-point Fast Fourier Transform (FFT) processor employing a novel Mixed Radix algorithm using Rapid Single Flux Quantum (RSFQ) Logic. The proposed processor leverages the bit-slicing technique, offering enhanced flexibility and adaptability for diverse signal processing applications. The Mixed Radix algorithm optimizes the computational efficiency of the FFT process by dynamically selecting radix factors based on the input size. The reconfigurability of the processor allows it to efficiently handle various N-point FFT computations, making it suitable for a wide range of applications. The hardware architecture is tailored to exploit parallelism and resource sharing, maximizing throughput and minimizing latency. The slice factors used in this research are four radix - 2², 4 radix – 2³, four radix - 2⁴, two radix – 4 and two radix – 8 methods to built an 16 point FFT processor. The calculated latency of this research is 11.7 GHz for proposed bit sliced 16 – point DIT FFT. And this is achieved by i^th slice factor in bit slicing methods. A design of 256 – point FFT is demonstrated in this research article to compare with the existing research. 256 point is divided into two 128 – point and those 128 – point FFT is divided into four 32 point for reduction hardware utilization cost. The proposed design aims to reduce computation time, improve processor performance, and minimize hardware costs while enabling through synchronous clock operation extended to multiple N²-point.