A Novel Hybrid Dual Ramp Generator for Two-Step Single-Slope ADCs in CMOS Image Sensors

This paper presents the design of a novel hybrid dual ramp generator for a two-step single-slope analog-to-digital converter (TS SS ADC). In this circuit, an R-2R DAC has been designed to replace the R-string DAC in the traditional coarse ramp generator, as a result the resolution can be improved in the coarse ramp stage and the conversion time of hybrid dual ramp generator can be decreased. The proposed hybrid dual ramp generator with coarse resolution of 5bit and fine resolution of 6bit has been designed and implemented in a 110nm CMOS process. The simulation results show that it can generate an output ramp voltage range of 0-2V, with a conversion time of 2 μs at the clock frequency of 50 MHz.