Single-Event Upsets Due to n-Hits and p-Hits at the 3-nm Bulk FinFET Node

Differences in the physical structure of semiconductor regions under nMOS and pMOS transistors lead to different levels of charge collection due to incident ions. In this work, ions striking nMOS transistors (n-hits) and ions striking pMOS transistors (p-hits) are characterized for a variety of particle linear-energy transfer (LET) values to comprehend the difference in charge collection for evaluating single-event (SE) vulnerability. At a 3-nm node, n-hits contribute much more to SE upset (SEU) vulnerability than p-hits. Technology computer-aided design (TCAD) simulations were used to differentiate the charge collection mechanisms of n-hits and p-hits. Results illustrate that the reduced effect of the parasitic p-n-p bipolar junction transistor (BJT) and limited diffusion charge collection in the n-well lead to a greater contribution to SEU susceptibility by n-hits compared to p-hits.