Auto Digit Selection for Most Significant Digit First Multiplication

Performance in modern embedded systems, particularly those executing computation-intensive signal/image processing and machine learning algorithms, is critically dependent on the efficiency of multiplication operations. Serial multiplication offers key advantages in these resource-constrained environments, including low-memory usage and minimal interconnect complexity. The most significant digit first (MSDF) serial multiplication scheme further enhances efficiency by enabling early termination and supporting variable precision. It is ideal for embedded applications where power and performance are critical. This letter proposes an auto-selection scheme for MSDF multiplication, where product digits are generated as a byproduct of residual maintenance, leading to speed, cost, and power efficiency improvements. We demonstrate the implementation of serial-serial and serial-parallel multipliers, where the multiplier operand in the latter is fully available throughout the computation. Simulation and synthesis results, compared to the most relevant previous works, show reductions in delay (16% and 20%), area consumption (11% and 23%), and power dissipation (7% and 20%), making our approach well-suited for embedded systems requiring efficient, low-power multiplication hardware.