MATLAB-Based Performance Verification of 2.4-GHz All-Digital Sub-Sampling PLL with −125 dBc/Hz In-Band Noise

This paper presents a MATLAB and Simulink model for a 2.4 GHz All-Digital Sub-Sampling Phase-Locked Loop (ADSSPLL) which could meet the strict demands of IoT equipment. The proposed ADSSPLL uses Sub-Sampling Phase Detectors (SSPD) to replace the high-resolution Time-to-Digital Converter (TDC) and avoid using the frequency divider which could greatly improve the in-band noise and reduce the loop complexity. MATLAB and Simulink tools are used to verify the circuit performance of ADSSPLL. With the reference frequency at 50 MHz, the In-Band Noise is measured to −125 dBc/Hz@1 MHz, and it achieves a Root-Mean-Square (RMS) output jitter of 347 fs.