Design and Implementation of Array Multiplier Using 2-Bit Accurate and Approximate Adder

In this work, a design approach for array multipliers using approximate adders is presented. Our approach focuses on improving efficiency mainly in terms of resource usage and area. We have implemented multiplier by using 2-bit approximation adders and are used in 4-bit and 8-bit array multiplier configuration for the validation. Comparative results of these circuits with existing designs proves that our approach reduces resource usage and area by 10% however adding error by 5-10%. The designed approximate multipliers were tested on image processing algorithm implementation.