SecRiSBen: A RISC-V based SoC Benchmark for Evaluation of Security Verification Tools

With the globalization of the semiconductor industry, the widespread practice of outsourcing and integrating third-party hardware Intellectual Property (IP) in System-on-Chip (SoC) design methodology raises significant security concerns. Additionally, the growing popularity of the free and open RISC-V ISA standard in industry and academia exposes potential vulnerabilities. Furthermore, the lack of unified evaluation benchmarks hinders the development of SoC security verification techniques. In this paper, we introduce SecRiSBen- a RISC-V based SoC benchmark for evaluation of the security verification tools. We propose seven approaches to design hardware vulnerabilities and subsequently implant tens of vulnerabilities into various locations within the SoC. The prototype validation results demonstrate minimal performance impact and hardware overhead.