The advanced adder generated using modified square root with AND-OR invert logic

Addition, subtraction, multiplication, and division are employed in the microelectronic system. Addition is a fundamental mathematical operation and deemed suspicious, yet the other operations are derived from it. Mobile computing and interaction are a fast-growing technology; thus, a low-power VLSI system is proposed to boost arithmetic operators' efficiency. Adder subsystem innovation is a crucial concern in processing unit VLSI designs. The Error Tolerant Adder outperforms the other adders in power consumption, area, and propagation latency. Using the right computing paradigm to construct an error-tolerant adder from hardware affects performance measures, notably application accuracy. The proposed square root with AND-OR invert logic model represents the three basic adders by the new notion of tolerance for errors in digital VLSI design. For model extension, Kogge-Stone adders are utilized. The model optimizes power, area, and switching activity by improving conventional Kogge-stone adders utilizing Ripple Carry Adders (RCAs) with better selector unit and modified error tolerant adder selector-based design. Compared to approximation adders, the proposed approach decreases latency, power breakdown, and dispersion in a digital circuit, area, power delay product (PDP), energy-delay product (EDP), and area delay product (ADP). It also enhances peak-signal-to-noise ratio (PSNR) for picture blending applications.