Optimization and Debug of FIVR Parameters in Server SoC Power Delivery Network: A Post Silicon Approach with on-Die DFx

The proposed methodology of using internal DFx features in an SoC focuses on providing a non-intrusive, reliable, and scalable method of optimizing and debugging Fully Integrated Voltage Regulator (FIVR) parameters, independent of test and measurement equipment saving around $70,000 per test setup which impacts cost and time to market significantly. It enhances measurement accuracy due to its proximity to the FIVR sense points compared to measurements done through external test pads on the package. The validation coverage achieved with this technique promises optimal FIVR stability parameters, zero-customer escapes, and accelerated debug.