A Low-Jitter Fractional-N LC-PLL With a 1/4 DTC-Range-Reduction Technique

A fractional-N LC oscillator-based phase-locked loop (PLL) with a 1/4 quantization noise (QN) range reduction technique is proposed. Simple open-loop delay cells are used to generate 4-phase clocks and reduce the QN by a factor of 4 while the mismatches of the four phases are calibrated and covered by a single DTC. Designed in 40-nm CMOS process, the proposed PLL achieves 159-fs RMS-jitter with 2.6-mW power consumption, leading to –251.8-dB FoM.