Vertical Channel Transistor (VCT) for Advanced Logic and Memory Applications

With the device feature size scaling down continuously, vertical channel transistor (VCT) becomes promisingly attractive for IC manufacturing thanks to its structural benefits in decoupling gate patterning and junction engineering. On one hand, the vertically aligned bitline configuration makes it naturally suit for 4F2 DRAM cell application. On the other hand, its offerings of variant junction engineering and tight layout design provides VCT potential for SoC applications. In this paper, we will discuss the VCT design considerations for advanced logic and DRAM applications from viewpoints of asymmetrical source/drain engineering and off-state leakage mechanism by TCAD.