A 0.11-pJ/Bit True Random Number Generator Based on a Clocked Current-Starved Inverter

This paper presents a clocked current-starved inverter-based true random number generator (TRNG) in 65-nm CMOS. The design of the TRNG uses inverter noise amplification and quantification through a sense latch. We add two extra transistors to a regular inverter to construct a current-starved inverter, used to remove the bias of the raw TRNG sequence generated by charge injection and SL offset. An adaptive calibration algorithm in conjunction with successive approximation register logic provides the biasing to the clocked current-starved inverter. Our TRNG occupies an area of only 0.0026 mm²and scores an energy efficiency of 0.11 pJ/bit for a 10 Mb/s random sequence with a 0.5 V supply. It can operate efficiently across a 0.5-1.4 V. Our TRNG is able to pass all the National Institute of Standards and Technology tests without requiring post-processing.