Flip 3D (F3D): A Novel 3D Integration Technology with Dual-Side Integration Capabilities

In this work, we proposed the Flip 3D integration, a novel 3D technology with dual-side transistors and interconnects. Two layers of transistors and interconnects are formed on each side of wafer and back-to-back stacked, featuring a much more manufacturing-friendly process flow with low aspect ratio (AR). On transistor level, Flip-FET(FFET), a new stacking transistor architecture is enabled by F3D and experimentally demonstrated. Standard cell (STC) libraries with minimum 2.5 track height (2.5T) design are established, proving further scaling possibility and better intra-cell routability over CFET thanks to dual-side signal tracks. Due to smaller cell area and less parasitic, FFET outperforms CFET for both Fin and Nanosheet channels. New concepts of dual-side global interconnects are introduced and the P&R result of a RISCV32I core further validates the superiority of F3D integration. The F3D integration can be further extended to other complex circuits integration, such as memory stacking, memory to logic stacking, delivering great flexibility and extendibility for future's electronic applications.