Reverse-Engineering Optimization Techniques of High-Level Synthesis: Practical Insights Into Accelerating Applications With AMD-Xilinx Vitis

Modern AI applications contain computationally expensive sections. Accelerator cards and tools like AMD Vitis HLS leverage high-level synthesis (HLS) and hardware (HW) optimizations to create custom HW designs to accelerate them. Nevertheless, the learning curve is steep, even for those with previous knowledge of HW design, due to the complexity of the optimization techniques and limited information on their interactions and HW effects. This article quantitatively analyses the interactions of optimization techniques after reverse engineering Vitis’ optimization directives, both in isolation and in pairs. Over 150 experiments were conducted to investigate three distinct goals: 1) assessing pragma behavior and the rules governing pragma application and optimizations; 2) modeling Vitis HLS latency estimates; and 3) evaluating the impact of optimizations on design space exploration (DSE), specifically area and latency. These experiments involve different combinations and placements of optimizations in the loop and function hierarchy of the test bench. Our findings offer guidance on using Vitis pragmas and identify promising configurations for optimizing latency and area.