Clocked Gate Reduction With Clockless Gates in Technology Mapping for RSFQ Logic Circuits

Technology mapping is a process in logic synthesis for designing logic circuits. It converts an internal graph representation of logic functions into a gate-level netlist. This study proposes a method that involves introducing clockless gates proactively into resultant netlists of RSFQ logic circuits. Ordinary RSFQ circuits consist of clocked gates and necessitate path balancing. The usage of clockless gates working without clock inputs reduces the number of clocked gates and logic stages, which leads to a smaller clock distribution network. The capability of reducing the number of stages is essential to improve flexibility in the number of logic stages of designed circuits. The method introduces more clockless gates into the resultant netlist compared with our previous method instead of a longer clock period. It utilizes a specific library of supergates, that is, small single-output circuits with several logic gates, used in technology mapping. The library is generated by adding supergates that utilize clockless gates, except for their output parts, to an original library with no clockless gates. The method reduces the number of clocked gates to a greater extent than our previous method and gives designers a higher degree of flexibility in the number of logic stages. The evaluation results indicate that the number of clocked gates in netlists and logic stages is reduced by over 40% when compared with netlists without clockless gates.