Low Power CMOS Based Dual Edge Triggered Flip Flop Using LECTOR C-Element

In the presence of signal interference and glitches, Double-Edge Triggered Flip-Flops (DETFFs) experience a substantial rise in power consumption. To address this issue and achieve power efficiency, this paper focuses on low-power DETFF utilizing LECTOR C-elements. The enhanced C-element integrated into DETFF effectively mitigates input signal glitches, inhibits unwanted transitions within the DETFF, and reduces the transistor's charge and discharge frequencies. LECTOR Circuit integrates two self-controlled leakage control transistors along the route from the power supply to the ground. This placement strategically introduces extra resistance, effectively diminishing the leakage current in the pathway. Further the optimized LECTOR C-Element reduces the delay by 15%. The utilization of these self-controlled transistors represents a promising advancement in mitigating leakage issues, showcasing potential improvements in the efficiency of CMOS circuits. In contrast to other currently available DETFFs, the DETFF introduced in this study undergoes a single flip exclusively at the clock edge and reduces the power consumption by 20%. The simulations were carried out by varying the Vdd voltage for the circuit form 0.6V to 1.2V on Cadence Virtuoso using GPDK-90 library and have the simulation results.