Design of Long Signal Path Ternary Computational Blocks Using Dynamic and Pass Transistor Logic Based on Carbon Nanotube Field Effect Transistors

Recently, approximate computing and dynamic logic design techniques have been shown to be effective for energy consumption reduction in the design of CNFET -based ternary arithmetic circuits, such as ternary half adders, 1-trit multipliers, and full adders. In this paper, the use of such a design strategy is studied in order to design other large computational blocks. Due to the long delay paths in these large computational circuits, further modifications in the logic can enhance the performance in some scenarios. Subsequently, a dynamic ternary approach is presented, which can break the pass transistor path and improve the performance in long delay chains. The proposed circuit designs of an approximate dynamic ternary full adder and a 4:2 dynamic ternary compressor work correctly under various supply voltages, temperatures, and fan outs. HSpice simulations using the 32 nm Stanford CNFET model, also show a 10% to 85% reduction in energy usage or PDP and 24^% to 86% improvement in terms of EDP, respectively compared to previous methods. The proposed circuits NED, MED, PSNR, and SSIM in image multiplication have also been acceptable regarding previous research.