Comparison Between Hardware/Software Co-Design of RiscV Vector and Scalar Implementation of Deep Neural Networks

This paper compares a hardware/software co-design of a RiscV vector with a RiscV scalar implementation of a deep neural network (DNN). For the vector implementation, all building blocks of a DNN are vectorized and written in vector intrinsic coding format. Focusing more on the convolution function as the main source of the latency, this function is written in a special parallel processing-favor method in the vector intrinsic level to boost execution speed. For the comparison, a sample scalar RiscV core is selected and paired with a vector-based RiscV co-processor. Also, the same sample DNN is implemented only on the scalar processor to demonstrate the speedup better. The system was implemented and tested on a field-programmable gate array (FPGA). As a result, the vector implementation outperformed the scalar version by a factor of 3 in terms of latency by only negligibly increasing the utilized sources on the FPGA.