Comparative Design of Low Power Half Adder Using MGDIB and CMOS Techniques

With the growing demand for portable electronic devices and the Internet of Things (IoT), optimizing power efficiency and speed in digital circuit design has become increasingly critical. Arithmetic components, such as half adders, are fundamental to many digital architectures. This research presents a comparative study between a low-power half adder designed using the Modified Gate Diffusion Input (MGDI) technique is a variation of the Gate Diffusion Input (GDI) method, which reduces power consumption and transistor count and an enhanced version with an isolation buffer, termed MGDIB, against a conventional CMOS-based half adder. Circuit designs were implemented using 0.35μm CMOS technology and simulated in LTspice. The performance metrics evaluated include transistor count, leakage current, static power dissipation, and delay. The MGDI half-adder requires only 13 transistors, significantly fewer than the 18 transistors needed by the CMOS design. Furthermore, the MGDIB configuration achieves a substantial reduction in leakage current (0.33 nA compared to 9.81 nA in CMOS) and a shorter delay (0.051 ns compared to 0.52 ns in CMOS). However, the MGDIB half adder exhibits slightly higher static power dissipation (0.11 nW compared to 3.23 nW in CMOS). These findings demonstrate that the MGDI and MGDIB techniques offer substantial improvements in transistor efficiency, operating speed, and power reduction, making them promising approaches for modern digital circuit design.