Hardware Accelerator for CNN using Optimized Multiply Accumulate Structure

Convolution is a critical operation in FPGA-based hardware accelerators, yet existing designs often overlook FPGA’s inherent architecture, posing challenges for hardware resource efficiency. Despite previous attempts with approximate multipliers and convolution acceleration algorithms, accuracy loss and resource occupation lead to performance degradation. This work proposes resource efficient optimized accurate multipliers based on LUTs and carry chains for FPGA platforms. A generic multiply-accumulate structure is constructed, directly accumulating partial products from optimized radix-4 Booth multipliers, demonstrating a maximum $51 \%$ LUT reduction compared to Vivado area-optimized multipliers. The convolutional process unit achieves a ${3 6 \%}$ LUT reduction. This Multiply Accumulate (MAC) structure with distributed arithmetic achieves greater reduction in delay and high-speed operation. Implementation details include critical path delay, power, and resource usage calculations are done using Cadence software and Virtex 7 FPGA board in Xilinx Vivado 2021.2. The inherent advantages of using ASIC for development and its trade-offs are also discussed. Implementation details include the parameters like power, area, delay and data path of the main module used to classify the 28X28 pixel grayscale digits (0-9) in MNIST dataset using Recurrent Convolutional Neural Networks (CNN). The circuit is synthesized using Cadence Genus to obtain the schematic and its associated resource values, timing, power and area reports. The logic verification and output waveforms are obtained using Cadence Incisive Simulator.