Compact Bi-Directional PA-LNA Using Stacked Power Amplifier Enhancing Linearity and Stability

This article presents a compact Ka-band bi-directional power amplifier-low-noise amplifier (PA-LNA) utilizing a three-stack power amplifier (PA) in a 28-nm CMOS process. In the proposed PA-LNA, the input and output of the three-stack PA are cross-coupled with the output and input of the common-source (CS) low-noise amplifier (LNA). This configuration neutralizes the gate-drain capacitance of the LNA through the parasitic capacitance ( $C_{\text {para}.}$ ) of the three-stack PA, improving stability and gain in the LNA mode. Simultaneously, the three-stack PA achieves higher output power and gain in the PA mode. Moreover, since $C_{\text {para}.}$ of the transistors are connected in series, the transistor sizes for the PA and LNA can be selected asymmetrically, alleviating the tradeoff between linearity in the PA mode and dc power consumption in the LNA mode. Additionally, the output conductance of the off-state PA is enhanced by stacking more transistors and applying appropriate biasing to keep them in the off-state, leading to an improved noise figure (NF) in the LNA mode. Furthermore, transformer-based switching matching networks (MNs) enable fully bi-directional operation within a compact die area of 0.1 mm2. In the PA mode, the proposed PA-LNA achieves a peak gain of 20.4 dB with a 3-dB bandwidth of 8.1 GHz (27.3–35.4 GHz), a saturated output power ( $P_{\text {sat}}$ ) of 17.4 dBm, a peak power-added-efficiency (PAE) of 17.2%, and an error vector magnitude (EVM) of −32.0 dB with 256-quadrature amplitude modulation (QAM) at an 800-MBaud symbol rate and 7.6-dBm average output power. In the LNA mode, the proposed PA-LNA achieves a peak gain of 17.3 dB with a 3-dB bandwidth of 8 GHz (28.0–36.0 GHz), a noise figure (NF) of 5.3 dB, and an input third-order intercept point (IIP3) of 0 dBm.