Hierarchical Fault-Tolerant NoC Architecture for Reliable Communication

As multi-core systems continue to grow in complexity, Network-on-Chip (NoC) architectures have emerged as a scalable and efficient solution for managing on-chip communication. However, ensuring reliable communication in the presence of router faults remains a critical challenge, particularly for applications in safety-critical systems where failure can lead to catastrophic consequences. This paper proposes a novel fault-tolerant NoC architecture designed to improve reliability in multi-core systems. The proposed method divides the NoC into multiple regions, each managed by a dedicated Region Router (RR) and interconnected via a Centralized Router (CR). This hierarchical structure ensures that even in the presence of multiple faulty routers, data packets can be rerouted effectively, maintaining system functionality. We implement the proposed method on a Xilinx Virtex-7 FPGA and evaluate its performance in terms of latency, throughput, power consumption, and resource utilization. The experimental results demonstrate that the proposed method achieves a 15% improvement in system reliability with only a 3.2% increase in resource utilization, compared to the baseline NoC. Additionally, Mean Time to Failure (MTTF) is extended by 25%, while the latency remains within an acceptable range of 3.2 ns. These findings highlight the potential of our approach for use in safety-critical and high-performance computing systems, offering enhanced fault tolerance without significantly compromising performance.