U-Net Hardware Accelerator

This paper presents a novel hardware accelerator specifically designed for the U-Net architecture, a popular model in image segmentation tasks. The proposed accelerator is implemented using TSMC’s 90-nm CMOS technology, which allows for efficient power and area utilization. The performance of the accelerator is evaluated in the context of U-Net. The evaluation results demonstrate a throughput of up to 195 GOPs for the U-Net accelerators with only 0.4 mm² area resources and 3.85 mW power consumption. These results indicate that the proposed hardware accelerator conserves resources and significantly boosts processing capabilities, making it a valuable advancement for applications relying on U-Net.