Design of Hierarchical Cache With Hybrid SOT- and STT-MRAM in Multi-Core CPU Environments

In the modern CPU system, the architecture of multi-cores is preferred, which can effectively enhance the computing capability. However, the performance upgrading gained from on-chip caches in single-core versus multi-core scenarios is not always linearly increased. Substituting static random access memory (SRAM) with magnetic random access memory (MRAM) in computational systems can improve cache performance since MRAM shows the merits of low power, non-volatile, and high density. In this article, based on the reduced instruction set computer-five (RISC-V) instruction set framework, a novel simulation strategy is employed to evaluate the performance of a multi-core hybrid cache system (L1–L3 caches). By comparing the performance of spin-transfer torque MRAM (STT-MRAM), spin-orbit torque MRAM (SOT-MRAM), and SRAM in the multi-core environment, a quad-core CPU system with a three-tier cache structure is proposed, in which SOT-MRAM and STT-MRAM are used to replace L2 and L3 caches, respectively. Additionally, the cache coherence protocol of the optimized architecture is tailored for magnetic memory components in the four-core CPU system. The simulation results demonstrate that this hybrid cache system achieves 54.96% leakage power savings and 22.88% performance improvement compared to the SRAM cache system. The evaluation of the hybrid cache system aligns closely with real-world requirements and exhibits scalability.