Warpage and Stress Analysis in Molded 2.5D Package Chiplet Integration

With the slowing of Moore's Law, chiplet technology emerges as a cost-effective and scalable solution to the challenges of advancing semiconductor manufacturing. It allows for the integration of heterogeneous chiplets, each designed under optimal process technology nodes, to meet specific application requirements. 2.5D silicon interposer packaging platform has been widely used in heterogeneous chiplet integrated packaging to support high-end performance product requirements. In this study, we focused on2.5D package to evaluate structural and material solution at initial design stage. In this work, numerical FE models of molded 2.5D package was built-up. Simulations of different design of combo die layout configuration and interposer thickness were performed to assess warpage and ILD stress. The simulations demonstrated that the four smaller ASIC dies were combined into a single die or reduces interposer thickness could reduce the package warpage. However, they would exist combo die warpage and ILD stress risk. Key effects of different material properties are also performed through simulation analysis. The simulation results show that adjusting the mechanical properties of EMC and WUF could effectively reduce ILD stress and early-stage combo die warpage, positively impacting the reliability of the package. However, it has limited influence on the final package warpage. Future improvements could combine material adjustments with structural changes for a more comprehensive approach to minimizing both warpage and stress. Through optimization analysis, subsequently, a design guideline will be established based on the simulation results to facilitate future designs for molded 2.5D package chiplet integration.