Fracture Analysis of Micro-vias with Low to High Void Existence at Electroless Cu Plated Layers after Thermal Shock Reliability Cycle Test

The electronics manufacturing industry is demanding higher microvia densities and smaller microvia diameters. This is to achieve multi-functional yet compact devices. However, the downsizing movement would make the weak microvia (WMV) problem obvious, as thinner and smaller designs physically reduce the strength and durability of the devices. WMV cracks have been found primarily at the bottom of the microvia where the electroless copper plating layer is located. In our presentation at IMPACT 2023[1], the reliability of 3-layer double-sided packaging substrates with varying degrees of void presence in their electroless copper plated layers of 60 micron microvias was estimated by a -55°C x 15 min/150°C x 15 min thermal shock reliability cycle test. Reliability was estimated using the Weibull analysis method by the number of failed thermal shock cycles when the internal circuit broke. As a result, the package substrate with more voids in the electroless Cu plated layer was found to have lower reliability in the thermal shock cycle test (F(10%)=app. 500 cycles) than the package substrate with fewer voids in the electroless copper plated layer (F(10%) = app. 1000 cycles). In addition, strain concentrations in the microvia bottom areas where the electroless copper plated layers are located were confirmed by the finite element method simulation due to the discrepancies of the layered materials. The strain concentration is more obvious in the micro vias near the core layer of the packaging substrates.