RISC32-A: A Low-Power Asynchronous IoT Processor on FPGA With Adaptive Pipeline Structure

Field-programmable gate array (FPGA)-based sensor nodes are gaining popularity for Internet of Things (IoT) applications due to their flexible hardware reconfigurability. RISC32 is a recently proposed synchronous IoT processor, targeting the FPGA-based sensor nodes. However, its dynamic energy consumption is relatively high as its circuit components often activate with each tick of the global clock, irrespective of the actual need. RISC32-LP presented various power reduction techniques to enhance its energy efficiency, but it still necessitates the use of a constantly switching global clock in many parts of the system for synchronization. In view of that, this research work proposed a novel asynchronous processor design (RISC32-A) to significantly minimize the switching events in RISC32, thus lowering its overall dynamic energy consumption. Besides, this research work also proposed an adaptive asynchronous pipeline structure that allows selective pipeline stages to be dynamically skipped, merged, split, and stalled during the program run-time for optimal performance-energy tradeoffs. A novel pipeline stage skipping solution was introduced, which considers various instruction types and prevents wasteful data movement for the early-completed instructions. Additionally, a two-phase collapsible register handshake component with normally closed flip-flops was presented for enhanced dynamic power savings. Finally, a new pipeline halting solution was proposed to eliminate the decoding and forwarding hardware overheads found in the prior works. Experimental results show that the proposed RISC32-A can achieve an average reduction of $\approx 83.71\%$ and $\approx 65.98\%$ in dynamic energy consumption when compared to its synchronous counterpart (RISC32) and its optimal low-power synchronous counterpart (RISC32-LP), respectively.