Efficient Microprocessor Design Space Exploration via Space Partitioning

Design space exploration (DSE) has long been a very important topic in electronic design automation (EDA). As the diversity of applications and the complexity of integrated circuits have grown rapidly in recent years, conventional DSE frameworks become less effective and efficient. This is due to the time-consuming nature of design point evaluation and the challenge of exploring high-dimensional design spaces. To address these issues, this paper proposes a DSE framework for microprocessors with a novel multi-objective optimization algorithm to find optimal designs with fewer samples. The proposed algorithm utilizes space partitioning and Bayesian optimization to efficiently explore high-dimensional design spaces in microprocessors.