Design and Verification of DDR5 Subsystem Using UVM Methodology

This paper discusses the design and verification of a DDR5 subsystem using UVM methodology to achieve high data transfer rate. The current state of the electronics industry demonstrates a significant demand for improved DRAM performance, which is largely dependent on the performance of the DDR physical layer (PHY). The latest DDR5 JEDEC JESD79-SA and DFI standards address these industry needs and outline the features of advanced DDR5 PHY. UVM, in combination with SystemVerilog Assertions (SVA), is chosen as an effective solution to create a robust and reusable testbench for the digital data path of the DDR5 PHY. In this work, we follow a verification flow that begins with extracting specifications from the standards, followed by developing a verification plan and finally constructing a UVM verification environment using SystemVerilog to obtain Functional and code coverage.