Design and Timing Analysis of 32 Bit Floating Point Pipelined Multiplier

The pipelined multiplier is designed to handle 32-bit floating-point operands and employs a pipelined architecture for improved performance. This paper examines the Verilog implementation and timing analysis of pipelined multipliers using Vivado Tool, specifically focusing on the assessment of timing slack. Through separate evaluations, it discusses instances where timing constraints are met and violated for multiplier design. The design employs LUTs primarily for logic operations, with 82 Slice Registers for state storage and pipelining. The total on chip power consumption is of 0.119 W. Positive slack of 2.546 ns is recorded and by analyzing timing slack, the paper provides valuable insights into the timing performance of both architectures, aiding in understanding their reliability and potential optimization avenues.