Tunable CMOS Synapse Spiking Neural Networks for Low-Power Deep Learning Power Systems

This paper presents the design of a fully integrated tunable CMOS synapse circuit for Spiking Neural Networks. By using multiple-gated transistor configuration in the tunable CMOS synapse an additional branch provide control where the synaptic output current time-constant is tuned. The effect of changing the multiple-gated transistor bias voltage from 0.25V to 0.45V tunes the spiking output current exponential time-constant range by 200 ms as shown in simulation results. By tuning the decaying exponential time-constant with multiple-gated transistor configuration, the proposed tunable CMOS synapse captures the dynamic nature of biological synapses.