A High dv/dt Immunity Complementary Current Compensation Level Shift Circuit for GaN Half-Bridge

A novel complementary current compensation level shift circuit is proposed to cope with the dv/dt problem in the GaN half-bridge structure. The level shift circuit converts the input voltage of 0~5V to the output voltage of 35 ~ 40V. It uses a 40V HVMOS to realize the signal conversion, which is based on the current mirror for signal transmission. The compensation circuit ensures that the level shift circuit outputs the correct logic. This design is based on a 0.35µm BCD process and is simulated and verified at an operating frequency of 1MHz. The results show that the positive dv/dt immunity is greater than 350V/ns, the negative dv/dt immunity is great, the rise transmission delay is 1.494ns and the fall transmission delay is 1.345ns. Verified at different process corners and temperatures, the positive dv/dt immunity is all greater than 350V/ns. A high dv/dt immunity, low-ripple level shift circuit is realized.