A Five-Stage Pipelined Processor Circuit Design Based on RISC-V

In the field of processor design, RISC-V instruction set has the advantages of modularity, low power consumption, high performance and easy scalability. Five-level pipelining has significant advantages in improving processor utilization and resolving performance bottlenecks. This paper presents the design principle, implementation method and performance evaluation of a five-stage pipeline processor based on RISC-V. The pipelined processor circuit implements the overlapping execution of instructions by adding pipelined registers between each subprocess, holding all the information that the previous stage wants to pass to the next stage. Improve instruction throughput, shorten program execution time, improve processor performance, realize the simulation verification of single instruction.