Secure Encryption and Decryption Circuit on 8T1C Structure-Based Charge Accumulation and Dissipation

To solve the large resource overhead and risk problems of traditional encryption and decryption technologies. This paper presents a secure computing scheme of 8T1C structure based on charge accumulation and dissipation which is used to implement low-cost encryption and decryption circuits. Firstly, the scheme uses the characteristics of capacitor charge accumulation and dissipation to complete the XOR encryption. Decryption of data is performed by dynamically charging and discharging the load capacitor. Secondly the 8T1C SRAM unit structure is designed in combination with the Static Random-Access Memory Physical Unclonable Function (SRAM PUF) structure. The encryption and decryption operations are built into the storage unit to reduce the hardware resource overhead, by integrating additional MOS tubes and capacitors. Finally, the encrypted data is reshaped by the sense amplifier and stored in the same unit. The function of safe data storage is realized through hardware reuse of circuit resources. The security encryption and decryption circuit is simulated and verified In the TSMC 65nm process. The experimental results show that the designed encryption and decryption circuit structure can confuse the traces of the original data and recover the original information content in the decryption process. PUF key uniqueness is 50.31%, randomness is 99.9%, and it has passed the NIST randomness test. Under the working environment of -50 °C~125°C and 0.8V to 1.5V, the worst bit error rate is 7.6%, which can be applied to the security encryption field of the Internet of Things.