A Digital Low Drop Out (DLDO) Regulators with Transient Enhancement

Based on the DLDO structure employing a coarse-fine dual-loop design, this paper proposes a transient-enhanced auxiliary loop. The transient-enhanced auxiliary loop leverages the fast response capability of flip-flop circuits to achieve rapid transient response. The DLDO regulator is implemented using a 55nm CMOS process, with a load capacitance of 400pF. Under typical process conditions and room temperature simulation, the static current measures 7.15µA. The reference voltage is set at 0.7V, with a maximum load current of 20mA and a minimum of 4mA. During load transitions from 4mA to 20mA, the switching time is 30ns, resulting in a downshoot voltage of 62.78mV and a recovery time of 0.55µs. Conversely, when transitioning from 20mA to 4mA, the switching time remains 30ns, with an overshoot voltage of 81.3mV and a recovery time of 0.74µs. The current efficiency, as depicted in the figures, reaches 99.9%.