A Computing-in-Memory Architecture with High Precision and High Linear MAC Operations

This paper presents a computing-in-memory (CIM) architecture with high precision and high linearity multiply-and-accumulate (MAC) operations for deep neural networks (DNNs). The CIM array is composed of 12T SRAM cells, and the 8-bit input is divided into high 4-bit and low 4-bit, which are respectively fed into the cells of two adjacent columns. The multiplication results of the cells are accumulated on the compute bit lines (CBLs) and quantized by 4-bit Single-Slope analog-to-digital converters (SS ADCs). In the UMC 110nm process with a power supply of 1.2V, the circuit implements convolution operations with 8-bit input and 8-bit weight for a 3×3 convolution kernel, resulting in a 20-bit full precision output. The simulation results indicate that the proposed CIM architecture achieves a maximum nonlinearity error of only 0.83% for MAC operations, demonstrating high linearity. Moreover, it ensures excellent linearity and accuracy of output results in the presence of process, voltage, and temperature (PVT) variations.