A 760uW 1.83GHz PLL Using a Single-Ring Oscillator-Based Integrator with Background Frequency Calibration

A phase-locked loop (PLL) utilizing a single ring oscillator-based integrator and background frequency calibration is presented. The in-band phase noise and power efficiency of the PLL are improved by introducing an integrator based on a single ring oscillator. By employing background frequency calibration, the PLL demonstrates robustness against process, supply voltage, and temperature variations. In addition, a source-switched charge pump with reverse sub-threshold leakage current suppression are used to improve reference spur. Designed in 55 nm CMOS process, the PLL has a power consumption of 760 uW at 1 V supply voltage, a phase noise of $111 \text{dBc} / \text{Hz}$ at an offset frequency of 1 MHz, and a lock time of less than 0.8us.