A Multi-Level Verification Method for a Quad-Core RISC-V SoC

Verification is a time-consuming and resource-intensive task in System-on-Chip (SoC) design. However, a single verification method often fails to effectively meet diverse verification needs. In this paper, we present a multi-level verification method that divides SoC functional verification into the module level, the connectivity layer, and the chip level. At the module level, the Universal Verification Methodology (UVM) is used to verify the function of each module. At the connectivity layer, the formal verification is employed to check connectivity and correctness. At the chip level, the coroutine co-simulation testbench (cocotb) is used to verify the overall function of the SoC. By leveraging the advantages of various verification methods at different levels, the corresponding challenges are addressed. We applied this method to verify a quad-core RISC-V SoC and achieved significant reductions in verification time.